Verilog
Instructor name
- 120+ Students Enrollred
- (136) 4.5/5
What is Verilog
Verilog is a high-level hardware description language used to design and describe electronic systems. It allows engineers to model digital circuits at various levels of abstraction, from behavioural to structural, making it a versatile tool in the realm of digital design. Verilog is commonly used in the design and verification of integrated circuits (ICs), field-programmable gate arrays (FPGAs), and other digital systems.
Purpose of Verilog
Verilog course is to equip participants with the knowledge and skills needed to effectively design, simulate, and synthesize digital circuits using Verilog. Through lectures, hands-on exercises, and projects, students learn the syntax and semantics of Verilog, understand different modeling styles, and gain proficiency in writing efficient and reliable code. Additionally, they learn how to use simulation and synthesis tools to verify and implement their designs.
How it is useful to people if they take the course
Taking a Verilog course prepares individuals for careers in fields such as electronic design automation (EDA), semiconductor design, embedded systems development, and digital signal processing. With the proliferation of electronic devices and technologies, proficiency in Verilog opens up numerous career opportunities and enables individuals to contribute to the advancement of technology in areas such as telecommunications, automotive electronics, consumer electronics, and more.
Moreover, Verilog proficiency is often a prerequisite for advanced courses and research in digital design and electronic engineering, making it a valuable asset for students pursuing higher education in these fields. Overall, a Verilog course equips individuals with essential skills and knowledge to thrive in the fast-paced and ever-evolving field of digital design.
Module 1 - Verification Guidelines and Data Types
1.1 Verification Guidelines – Verification Process & Basic Test Bench Functionality
1.2 Directed Testing
1.3 Methodology Basics
1.4 Functional Coverage & Test Bench Components
1.5 Stimulation Environment Phases, Maximum Code Reuse
1.6 Data Types – Built – In Data Types
1.7 Fixed Arrays & Dynamic Arrays
1.8 Queues, Associative Arrays
1.9 Linked Lists, Array Methods & Choosing a Storage Types
1.10 Creating new types with typedef
1.11 Creating User – Defined structures
1.12 Type Conversion, Enumerated types
1.13 Constants & Strings
1.14 Expression Width
Module 2 - Routines and Connecting the test bench & design
2.1 Procedural Statements, Tasks & Functions and Void Functions
2.2 Returning Statements, Returning from Routine
2.3 Local Data Storage & Time Values
2.4 Separating the test bench & design
2.5 Interface Constructs & Stimulus timing
2.6 Interface driving and sampling
2.7 Top-level Scope
2.8 Module Interactions, System Verilog assertions
Module 3 - Basic OOP
3.1 Introduction
3.2 Defining a Class
3.3 Creating new Objects & Object De – Allocation
3.4 Static Variables vs. Global Variables
3.5 Class Methods, Defining Methods outside of the class
3.6 Scoping Rules & Dynamic Objects
3.7 Copying Objects & Public vs Private
3.8 Building a test bench
Module 4 - Randomization
4.1 Randomization in System Verilog
4.2 Constraint Details, Solution Probabilities
4.3 Controlling Multiple Constraints blocks
4.4 Valid Constraints & In – line Constraints
4.5 The Pre-Randomize and Post-Randomize Functions
4.6 Common Randomization Problems
Module 5 – Inter Process Communication and Functional Coverage
5.1 Events, Semaphores & Mailboxes
5.2 Coverage Types & Functional Coverage Strategies
5.3 Anatomy of a Cover Group & Triggering a Cover Group
5.4 Data Sampling & Cross Coverage
5.5 Generic Cover Groups & Coverage Options
5.6 Analysing Coverage Data
5.7 Measuring Coverage Statistics during Stimulation
Course Price - 7000/-
- Duration
- 45 hours
- Lectures
- 15
- Level
- Intermediate
- Language
- English
- Certificate
- Yes
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